PISCATAWAY, N.J., March 05, 2020 (GLOBE NEWSWIRE) --
OpenCAPI Specifications
The OpenCAPI Consortium today announced the release of four new specifications including: 1) OpenCAPI 3.0 Transaction Layer Architecture for accelerator end point device development, 2) OpenCAPI 3.1 Transaction Layer Architecture for memory buffer device development built around the Open Memory Interface (OMI) to enable evolving memory technologies and standards, 3) OpenCAPI Ready for those companies that wish to perform limited self-certification to have their devices designated as being OpenCAPI Ready™, and 4) OpenCAPI 25 Gbps PHY Signaling Specification for users to certify their OpenCAPI 25 Gbps electrical interface. These specifications are now released formally to all OpenCAPI members at the OpenCAPI Consortium website: https://opencapi.org/ Non OpenCAPI members can download the Transaction Layer Architecture specifications for study purposes.
OpenCAPI Ecosystem Growth
To further advance the growth of the ecosystem, OpenCAPI members are releasing reference designs on GitHub to kickstart developers. Designs released to date include: 1) OpenCAPI 3.0 Endpoint Device, 2) Example OMI Host Design, 3) Example OMI Device with 2 DDR4 memory ports, and 4) OpenCAPI Acceleration Framework (OC-Accel) to develop endpoint accelerators using higher level programming languages. These are located on the GitHub website: https://github.com/OpenCAPI
Engineering Notes
In addition, OpenCAPI members have released engineering notes for developers including: 1) TLX Reference Design Supporting Documentation to accompany the OpenCAPI 3.0 Endpoint Device Reference Design, 2) OMI Reference Design Workbook to accompany the example OMI Device Reference Design, and 3) OpenCAPI Acceleration Framework Supporting Documentation.
About OpenCAPI
The OpenCAPI Consortium is an open forum to manage the OpenCAPI specification and ecosystem. OpenCAPI is a not-for-profit organization formed in October 2016 by OpenCAPI Board Members AMD, Google, IBM, Mellanox Technologies and Micron to create an open coherent high performance bus interface based on a new bus standard called Open Coherent Accelerator Processor Interface (OpenCAPI) and grow the ecosystem that utilizes this interface. This initiative is being driven by the emerging accelerated computing and advanced memory/storage that requires a technical solution that is openly available.
To learn more about the OpenCAPI Consortium, go to https://opencapi.org
Media Contact:
Joni Sterlacci
j.sterlacci@ieee.org
732-562-5464