SAN JOSE, Calif., Jan. 28, 2008 (PRIME NEWSWIRE) -- Magma(r) Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software, today announced Talus(r) QDRC, a physical design verification product that improves productivity and time to market for 65- and 45/40-nanometer (nm) designs by identifying and correcting design rule violations during implementation. Unlike prevailing DRC methods that require streaming data from an implementation database -- resulting in missed errors that require design rework, lengthening the design cycle of today's complex devices significantly -- Talus QDRC decreases overall design costs by addressing Design Rule Check (DRC) problems before they delay design tapeout. Talus QDRC is deploying today on 65- and 45/40-nm designs.
Magma customers will present case studies on use of Talus QDRC and Magma engineers will present a Talus QDRC tutorial at MUSIC, Magma's users group conference, Feb. 27-28 in Santa Clara. Visit www.magma-da.com/MUSIC.html for more information on MUSIC.
"When designs were less complex, contained fewer IP blocks and used less restrictive design rules, running DRC sign-off late in the flow did not lead to design rework. But with today's complex designs, the design rework that approach requires is prohibitively expensive," said Kevin Walsh, vice president of marketing for Magma's Physical Verification Business Unit. "Running DRC earlier in the implementation flow easily corrects errors, avoiding the expense of rework."
Talus QDRC operates systematically during implementation, reducing the post-implementation DRC sign-off effort and shortening the final physical design verification stage of chip development. Talus QDRC has access to all layout layers with IP reference views to identify common problems that can affect final sign-off downstream in the flow, including LEF-versus-GDS mismatch; problems with metal fill; and open/short detection. It also saves cycle time by eliminating the need to stream data out of and back into the implementation flow for DRC or layout versus schematic (LVS) analysis.
"Talus QDRC improves designers' productivity by eliminating DRC problems early in the flow. The design implementation teams using Magma have better visibility and control of their designs as they move to tapeout because potential DRC errors are eliminated during implementation," Walsh said. "Magma's unified data model and the power of Talus QDRC combine to give our users data abstractions of the right layers at key points in the flow that enable efficient and accurate DRCs during implementation. Current methods are not equipped to handle DRCs during implementation, which causes expensive reruns that delay time to market."
Talus QDRC is easy to implement in virtually any existing flow: the world's leading foundries support Talus QDRC with foundry-certified design rule runsets, and a runset translator enables users to run Calibre rules during Talus implementation by reading and converting Calibre decks to produce Talus QDRC rules.
Speeding Time and Minimizing Costs of Implementing DRC-Clean Designs
Talus QDRC helps minimize the time and costs of implementing DRC-clean designs. It allows designers to run checks using foundry-certified design-rule runsets directly on blocks without having to stream out the data in GDSII format. Reference-level IP views of all GDS layers can be generated making debugging easy. A powerful debugging user interface exposes DRC issues systematically. ECO changes are handled with a new incremental capability that uncovers DRC checks in minutes rather than hours or days, working on just the changed portion of the design. Talus QDRC's unique pipelined architecture scales linearly with the addition of more CPUs, shortening execution times without requiring costly machines.
"Typical 65-nm blocks range in size from 1 million to 2 million instances with physical GDSII file sizes ranging from 1.5 to 2.5 gigabytes, and the typical runtimes to check the design for rule violations can range from 5 to 7 hours. These checks are run four or five times on each block. So you might have to spend up to 35 hours per block running checks," Walsh said. "And that doesn't include the time it takes to back annotate the markers and make corrections in the implementation database. As the design approaches completion, the size can increase to more than 10 million instances with a GDSII file size of more than 7 gigabytes. This back-end checking flow can add weeks to the design cycle.
"The runtime and hardware cost at 45 nm or 40 nm will be even worse than at 65 nm," Walsh added. "Design size will increase to nearly 20GB. DRC processing times will explode and move beyond the single-day turnaround threshold. To meet this turnaround explosion, the DRC engines will respond by using multiple CPUs and threading the operations. But this will drive hardware costs up -- because threading still requires a single processor to control and consolidate results, the runtimes do not scale linearly. And because the older engines require that the data model be memory resident to resolve the checks that are common at 65 nm and at 45 nm or 40 nm, this large memory footprint will dramatically increase the overhead project costs in order to deploy these costly machines."
Talus QDRC is available now. For more information on the benefits of running DRC during implementation for today's advanced designs, including how DRC runs taking days or weeks can be shortened dramatically, download the whitepaper, "Moving Sign-off into the Implementation Flow with Talus and Quartz(tm) DRC", available from the Magma website at www.magma-da.com/whitepapers.html#QDRC.
About Magma
Magma's software for designing integrated circuits (ICs) is used to create complex, high-performance chips required in cellular telephones, electronic games, WiFi, MP3 players, DVD/digital video, networking, automotive electronics and other electronic applications. Magma's EDA software for IC implementation, analysis, physical verification, circuit simulation and characterization is recognized as embodying the best in semiconductor technology, enabling the world's top chip companies to "Design Ahead of the Curve"(tm) while reducing design time and costs. Magma is headquartered in San Jose, Calif., with offices around the world. Magma's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com.
Magma and Talus are registered trademarks, and Quartz and "Design Ahead of the Curve" are trademarks of Magma Design Automation Inc. All other product and company names are trademarks or registered trademarks of their respective companies.
Forward-looking Statements:
Except for the historical information contained herein, the matters set forth in this press release, including statements that Talus QDRC reduces turnaround time and cuts costs of nm ICs and about the features and benefits of Magma's software are forward-looking statements within the meaning of the "safe harbor" provisions of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially including but not limited to the ability of Magma's products to produce the desired results and the company's ability to keep pace with rapidly changing technology. Further discussion of these and other potential risk factors may be found in Magma's public filings with the Securities and Exchange Commission (www.sec.gov). The company undertakes no additional obligation to update these forward-looking statements.
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