AndesCore(TM) N9 High Performance Efficiency, Low Interrupt Latency Support Customer's SoC 4-in-1 Wireless Connectivity: 2.4GHz Wi-Fi/Bluetooth; 5GHz Wi-Fi; GPS; and FM
HSINCHU, TAIWAN--(Marketwired - November 14, 2017) - Andes Technology Corporation (
"We are thrilled to be integrated into this leading Taiwan IC design house's chip," said Andes President Frankwell Jyh-Ming Lin. "In highly integrated chips like this SoC, our ability to provide 3.6 CoreMark/MHz compute performance while consuming 80% of the program memory size of its competitors gives Andes a distinct advantage. Furthermore, the N9 allows designers to configure its performance, power, and size to match his/her application's requirement more precisely. These capabilities have enabled the N9 to win a number of wireless connectivity designs."
About the Home Smart Speaker Market
An Andes study done this year projected that the world's tier one on-line sellers could have more than 800 million active customers globally by 2022. "Assuming 30 percent adoption rate in the U.S. and 20 percent internationally, this would mean 55 million devices sold that year," the study concluded. "Assuming a two year-replacement cycle, and $75 average selling price, this would generate revenue of $4 billion in 2022."
About the AndesCore™ N9 Family
The AndesCore N9 Family is intended for deeply embedded applications that require high performance efficiency and optimal interrupt response features, including wireless networking and sensors as in microcontrollers, automotive electronics, and industrial control systems. The low-power N9 Family of processors features compact program size, low gate count, low interrupt latency, and low-cost debug. The processor family provides superior performance and excellent interrupt handling response while meeting the challenges of low dynamic and static power constraints. The AndesCore N9 Family of CPU cores implement v3, the patented AndeStar™ 32-bit RISC CPU architecture. The designers can configure certain parameters to adjust the desired CPU's performance, power and gate count. For example, the N9 core can be configured with 16 or 32 general registers, two or three read ports on the register file, one or two write ports, a fast or a small multiplier, a 24-bit or 32-bit address space, and different bus (APB, AHB, AHB-Lite, or AXI) interfaces to connect to the rest of the system. Its bigger cousin N10 Family supports caches and an optional floating-point coprocessor.
Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. The company delivers the best super low power CPU cores with integrated development environment and associated software and hardware solutions for efficient SoC design.
To meet the demanding requirements of today's electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers' needs for quality products and faster time-to-market. Andes Technology's comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications.
For more information about Andes Technology, please visit http://www.andestech.com/.
Andes Technology Corporation
510 449 8634