DVCon U.S. 2021 Announces Call for Panel, Short Workshop and Tutorial Proposals

GAINESVILLE, Fla., Sept. 03, 2020 (GLOBE NEWSWIRE) -- The 2021 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announces its call for panel, short workshop, and tutorial proposals. The conference will be held virtually March 1-4, 2021. DVCon U.S. will offer attendees a combination of recorded presentations and live Q&A to provide an interactive, high quality virtual experience.

Panels
DVCon U.S. will host two panel discussions.  The one-hour panels should be lively, can be controversial, and should provoke engaging discussion on a topic of interest to the community. 

Suggested topics include:  Experiences using design and/or verification IP for SoC development; Experiences applying machine-learning techniques; Experiences adopting functional-safety related standards such as ISO26262, DO-254, etc.; Design and verification sign-off and closure; Dealing with the technical and logistical challenges of multi-site projects; Developing, adopting and proliferating new standards; Experiences deploying a verification methodology library, especially the deployment of UVM; Designing and/or verifying complex ASICs and FPGAs using multiple HDLs and/or HVLs in a design cycle; Organizational and technological challenges in a pandemic; What will our industry look like in 5-10 years given the COVID-19 disruption?

More information and guidelines can be found here.

Sponsored Short Workshops
Short workshops are sponsored 60-minute sessions.  DVCon offers short workshops to provide more opportunities for participation from companies and exhibitors, especially smaller organizations, at an affordable level. 

Suggested topics include: SystemVerilog for Verification and/or Design; SystemC /C/C++ Design and/or Verification of systems; SoC and Software-driven Verification; Assertion-based Verification. SystemVerilog Assertions, PSL, etc.; Coverage-driven Verification; High-level Synthesis; Low-power Design and Verification techniques; Secure/Encrypted IP-based SoC design methods; Debug for design and verification; Mixed-signal modeling and verification; Transaction Level Modeling (TLM), ESL Design, and IP integration (IP-XACT); Functional Safety; Security; Embedded software verification; Hardware/Software Co-development; Verification Productivity Methods; Formal Methodology and Static Analysis; Emulation; Post SI Debug; FPGA Prototyping; Moving from proprietary solutions to standards-based design and verification; Portable Stimulus; Application-specific design verification challenges, techniques; Machine Learning driven techniques; Open source hardware/software/architecture.

Proposals should be an abstract of the short workshop, two-five paragraphs and no more than 1,000 words. For more information, including pricing visit here.

Sponsored Tutorials
The two-hour DVCon U.S. tutorials are available to all attendees and are included in full conference registration. The Committee is seeking sponsored tutorial topics that are current, have a high-level of interest and offer strong continuing educational content.

Suggested topics include: SystemVerilog for Verification and/or Design; SystemC /C/C++ Design and/or Verification of systems; SoC and Software-driven Verification; Assertion-based Verification, SystemVerilog Assertions, PSL, etc.; Coverage-driven Verification; High-level Synthesis; Low-power Design and Verification techniques; Secure/Encrypted IP-based SoC design methods; Debug for design and verification; Mixed-signal modeling and verification; Transaction Level Modeling (TLM), ESL Design, and IP integration (IP-XACT); Functional Safety; Security; Embedded software verification; Hardware/Software Co-development; Verification Productivity Methods; Formal Methodology and Static Analysis; Emulation; Post SI Debug; FPGA Prototyping; Moving from proprietary solutions to standards-based design and verification; Portable Stimulus; Machine Learning driven techniques; Open source hardware/software/architecture.

Proposals should be an abstract of the tutorial, two-five paragraphs and no more than 1,000 words. For more information, including pricing, visit here.

Deadlines for panels, tutorials, and workshops
The deadline to submit panel, tutorial and short workshop proposals is September 22, 2020.

About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DVCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.