GlobeNewswire: eSilicon Corporation Contains the last 10 of 44 releaseshttp://www.globenewswire.com/External?Length=42024-03-29T14:38:47ZGlobeNewswirehttp://www.globenewswire.com/External?Length=4newsdesk@globenewswire.com (NewsDesk)https://www.globenewswire.com/news-release/2019/11/14/1947147/0/en/SC19-eSilicon-to-Demonstrate-7nm-58G-DSP-Based-SerDes-Over-Five-Meter-Samtec-Cable-Assembly.html?f=22&fvtc=4&fvtv=49806SC19: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Five-Meter Samtec Cable Assembly2019-11-14T13:00:00Z<![CDATA[SAN JOSE, Calif., Nov. 14, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, and Samtec, a leading global manufacturer of electronic interconnect solutions, will demonstrate eSilicon’s 7nm 58G DSP-based PAM4/NRZ SerDes capabilities for challenging data center applications over a five-meter Samtec cable assembly.]]>https://www.globenewswire.com/news-release/2019/11/11/1944718/0/en/eSilicon-to-be-Acquired-by-Inphi-and-Synopsys.html?f=22&fvtc=4&fvtv=49806 eSilicon to be Acquired by Inphi and Synopsys 2019-11-11T13:33:15Z<![CDATA[Acquisition by Inphi with certain assets sold to Synopsys Acquisition by Inphi with certain assets sold to Synopsys]]>https://www.globenewswire.com/news-release/2019/09/22/1918779/0/en/eSilicon-Announces-Availability-of-7nm-High-Bandwidth-Interconnect-HBI-PHY-for-Die-to-Die-Interconnects.html?f=22&fvtc=4&fvtv=49806eSilicon Announces Availability of 7nm High-Bandwidth Interconnect (HBI+) PHY for Die-to-Die Interconnects2019-09-22T04:00:00Z<![CDATA[The PHY supports 2.5D applications such as silicon interposers and silicon bridges for system-on-chip (SoC) to chiplets and SoC partitioning The PHY supports 2.5D applications such as silicon interposers and silicon bridges for system-on-chip (SoC) to chiplets and SoC partitioning]]>https://www.globenewswire.com/news-release/2019/09/19/1918228/0/en/CORRECTING-and-REPLACING-eSilicon-Corporation.html?f=22&fvtc=4&fvtv=49806CORRECTING and REPLACING -- eSilicon Corporation2019-09-19T17:38:32Z<![CDATA[SAN JOSE, Calif., Sept. 19, 2019 (GLOBE NEWSWIRE) -- In a release issued under the same headline today by eSilicon Corporation, please note that in the headline of the release, it should be Seven-Meter and Five-Meter Samtec Cable Assemblies, not Seven-Meter and Three-Meter as previously stated. Additionally, in the third paragraph, it should be two 67cm AcceleRate® Slim Body Cable Assemblies, not 0.670cm as previously stated. The corrected release follows:]]>https://www.globenewswire.com/news-release/2019/09/19/1917903/0/en/ECOC-2019-eSilicon-to-Demonstrate-7nm-58G-DSP-Based-SerDes-Over-Seven-Meter-and-Three-Meter-Samtec-Cable-Assemblies.html?f=22&fvtc=4&fvtv=49806ECOC 2019: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Seven-Meter and Three-Meter Samtec Cable Assemblies2019-09-19T12:00:00Z<![CDATA[SAN JOSE, Calif., Sept. 19, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, and Samtec, a leading global manufacturer of electronic interconnect solutions, will demonstrate eSilicon’s 7nm 58G DSP-based PAM4/NRZ SerDes capabilities for two challenging data center applications including an industry-first use of a seven-meter cable assembly from Samtec.]]>https://www.globenewswire.com/news-release/2019/09/12/1915156/0/en/AI-Hardware-Summit-2019-Booth-to-Booth-eSilicon-58G-DSP-Based-SerDes-Demonstration-Over-a-Five-Meter-Samtec-Copper-Cable.html?f=22&fvtc=4&fvtv=49806AI Hardware Summit 2019: Booth-to-Booth eSilicon 58G DSP-Based SerDes Demonstration Over a Five-Meter Samtec Copper Cable2019-09-12T20:34:03Z<![CDATA[SAN JOSE, Calif., Sept. 12, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will partner with Samtec, a leading global manufacturer of electronic interconnect solutions, to deliver a rare booth-to-booth long-reach SerDes demonstration at AI Hardware Summit 2019.]]>https://www.globenewswire.com/news-release/2019/08/15/1902553/0/en/eSilicon-to-debut-AI-Accelerator-software-and-a-new-chiplet-model-at-Hot-Chips-2019.html?f=22&fvtc=4&fvtv=49806eSilicon to debut AI Accelerator software and a new chiplet model at Hot Chips 20192019-08-15T13:10:13Z<![CDATA[New software maps high-level AI workloads to eSilicon’s neuASIC modular AI ASIC IP platform]]>https://www.globenewswire.com/news-release/2019/06/20/1871607/0/en/eSilicon-Samtec-and-Wild-River-Technology-Offer-High-Performance-Communications-Webinar.html?f=22&fvtc=4&fvtv=49806eSilicon, Samtec and Wild River Technology Offer High-Performance Communications Webinar2019-06-20T06:00:00Z<![CDATA[Technology and collaboration required to deliver high-performance communications will be presented Technology and collaboration required to deliver high-performance communications will be presented]]>https://www.globenewswire.com/news-release/2019/06/06/1865698/0/en/eSilicon-to-Participate-in-Panel-Discussion-on-Chiplet-Design-Experience-at-a-Workshop-presented-by-the-Open-Compute-Project-OCP.html?f=22&fvtc=4&fvtv=49806eSilicon to Participate in Panel Discussion on Chiplet Design Experience at a Workshop presented by the Open Compute Project (OCP)2019-06-06T22:10:12Z<![CDATA[Workshop will focus on new Open-Domain Specific Architectures (ODSA) sub-group Workshop will focus on new Open-Domain Specific Architectures (ODSA) sub-group]]>https://www.globenewswire.com/news-release/2019/05/29/1854535/0/en/Google-and-eSilicon-at-DAC-2019-Doing-EDA-in-the-Cloud-Yes-It-s-Possible.html?f=22&fvtc=4&fvtv=49806Google and eSilicon at DAC 2019: Doing EDA in the Cloud? Yes, It’s Possible!2019-05-29T06:00:00Z<![CDATA[SAN JOSE, Calif., May 29, 2019 (GLOBE NEWSWIRE) -- Google and eSilicon will present eSilicon’s journey to ASIC and IP design in the cloud.]]>