SINGAPORE--5/26/2010, UNITED STATES--(Marketwire - May 25, 2010) - STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (SGX-ST: STATSChP) today announced that its low cost flip chip (LCFC) technology now utilizes copper column bump to deliver a powerful packaging solution at a dramatically reduced cost for its customers.
STATS ChipPAC's LCFC technology, introduced in 2009, has offered semiconductor companies the opportunity to have flip chip packages at price points below wire bond packaging due to its innovative routing efficient interconnection structure, simplified substrate design and cost effective mold underfill process. The unique structure of LCFC when combined with copper column bump achieves an even lower cost solution with higher routing densities and is scalable to finer bump pitches.
As technology continues to move toward finer silicon nodes to achieve increased functionality, input/output (I/O) densities are steadily increasing. The use of conventional solder bump makes the chip attach and underfill processes become more challenging and there is potentially an increased risk of electromigration due to the higher current density induced by the scaling of features. Copper column bumps enable a higher I/O density with a much finer pitch between the columns than standard solder bumps along with a higher resistance to electromigration. Although copper column is a hard bump material that can typically cause damage to low K (ELK) layers in finer silicon nodes, the LCFC interconnect structure dramatically reduces the mechanical stress on silicon sub-surface layers resulting in the elimination of the low K damage phenomenon commonly observed in sub-45 nm silicon modes.
"For applications requiring high I/O densities with a flip chip bump pitch below 150 microns, copper column bump provides a more effective interconnect structure compared with solder bumps," said Dr. Raj Pendse, Vice President of Technology Marketing, STATS ChipPAC. "By incorporating copper column bump into our low cost flip chip technology, STATS ChipPAC has expanded the range of applications for which high end flip chip technology can be deployed."
The incorporation of copper column bump has enhanced the LCFC offering in three main areas:
- Copper column bump enables a more dramatic simplification of the substrate features resulting in additional cost reduction.
- The LCFC interconnection structure with copper column bump is highly reliable and reduces mechanical stress on extra low K (ELK) layers in finer silicon nodes.
- The LCFC packaging solution using copper column bumps is Pb-free which supports the semiconductor industry's transition to using environmentally friendly materials in microelectronics.
Dr. Pendse continued, "Utilizing a copper column interconnect in low cost flip chip packaging achieves a lead-free solution that is reliable and scalable to very fine pitches and provides a natural migration path to solutions such as 3D, Through Silicon Via (TSV), micro bump and green solutions for the future."
STATS ChipPAC will be presenting the latest information on copper column, low cost flip chip and other innovative technologies such as embedded Wafer Level Ball Grid Array (eWLB) at the Electronic Components and Technology Conference that is being held June 1- 4th, 2010 in Las Vegas, Nevada.
Forward-Looking Statements
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; possible future application of push-down accounting; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilization; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; shortages in supply of key components; customer credit risks; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited ("Temasek") that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labor union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases, the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited ("SGX-ST"); and other risks described from time to time in the Company's filings with the U.S. Securities and Exchange Commission, including its annual report on Form 20-F dated March 5, 2010. You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.
About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.
Contact Information:
Investor Relations Contact:
Tham Kah Locke
Vice President of Corporate Finance
Tel: (65) 6824 7788
Fax: (65) 6720 7826
email: