HSINCHU, Taiwan, March 28, 2018 (GLOBE NEWSWIRE) --
WHO: Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32/64-bit embedded CPU cores, today announced that it will provide a panelist for the panel “The promises and pitfalls of RISC-V, from SOC Design Perspective” and exhibit during the Design & Reuse IP SoC Conference.
WHAT: Emerson Hsiao, Senior VP, Andes Technology USA Corp. will serve on the panel “The promises and pitfalls of RISC-V, from SOC Design Perspective” and the company will exhibit in booth 14.
WHEN: Wednesday, April 4th, 2018, 9 a.m. until 7 p.m. Panel begins 11:00 AM.
WHERE: Hyatt Regency, Santa Clara 5101 Great America Parkway, Santa Clara, Calif. Booth 14. To schedule a meeting e-mail jonahm@andestech.com.
About Andes
Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve worldwide rapidly growing embedded system applications. The company delivers the best super low power CPU cores with integrated development environment and associated software and hardware solutions for efficient SoC design.
To meet demanding requirements of today's electronic devices, Andes Technology delivers configurable software/hardware IP and scalable platforms to respond to customers' needs for quality products and faster time-to-market. Andes Technology's comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address the full range of embedded electronics products, especially for connected, smart and green applications.
For more information about Andes Technology, please visit http://www.andestech.com/
For more information, contact:
Jonah McLeod
Andes Technology Corp.
(510) 449-8634
jonahm@andestech.com