SAN JOSE, Calif., Sept. 12, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will partner with Samtec, a leading global manufacturer of electronic interconnect solutions, to deliver a rare booth-to-booth long-reach SerDes demonstration at AI Hardware Summit 2019.
What & When
58G SerDes Demonstration: eSilicon & Samtec Booths at AI Hardware Summit
Tuesday-Wednesday
September 17-18, 2019
Using Samtec ExaMAX® Backplane Connector paddle cards and a five-meter ExaMAX Backplane Cable Assembly, eSilicon will demonstrate the performance, flexibility and extremely low power consumption of its 7nm 58G DSP-based PAM4/NRZ SerDes.
This demonstration highlights the SerDes performance, robustness and architectural flexibility supporting independent data rates and protocols on each individual lane (e.g., 50G PAM4 Ethernet, 24G NRZ CPRI and proprietary protocols up to 58Gb/s).
A broad set of monitoring and diagnostic tools are available through the eSilicon SerDes evaluation module kit and its graphical user interface to control, observe and analyze signal quality and performance metrics across the link in real time, including:
- Bit-error rate (BER) monitor
- Eye diagram monitor
- Equalization capabilities
- Error histogram monitor with post-FEC estimator
About AI Hardware Summit
Computer History Museum
Mountain View, Calif., USA
The AI Hardware Summit USA is the first and only conference dedicated solely to the ecosystem developing hardware accelerators for neural networks and computer vision. Over 500 attendees are expected.
Nearly 40 companies—including hyperscalers, semiconductor companies, device manufacturers and the critical mass of AI hardware start-ups from across the globe—will present their approaches to processing machine learning training and inference workloads in both server and client computing.
About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 58G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com
Collaborate. Differentiate. Win.™
eSilicon is a registered trademark, and the eSilicon logo, neuASIC and “Collaborate. Differentiate. Win.” are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.
| Contacts: | ||
| Sally Slemons | Nanette Collins | |
| eSilicon Corporation | Public Relations for eSilicon | |
| sslemons@esilicon.com | nanette@nvc.com | |