MEDIA ALERT: Join Andes Principle Architect Dr. Thang Tran's Lecture, "Demystifying RISC-V Vector Extension"


Santa Clara, July 09, 2021 (GLOBE NEWSWIRE) --

What: Andes Technology Corp. will hold an on-line zoom Lecture. The hour long event will be the first of a 4-part lecture series on next-generation vector processor design. It will showcase a 5-stage pipeline and an 8-stage in-order superscalar vector processor based on Andes’ latest AndeStar™ V5 Architecture. Both have design wins at major TSMC foundry customers.

Who: Dr. Thang Tran, Principal Architect and veteran of high-performance computing (HPC) at Andes Technology Corp. will be the series' presenter. Dr. Tran is an industry expert in HPC development. He architected and designed the Andes RISC-V out-of-order (OOO) Vector Processor (VLEN/SIMD=512b) in 9 months using a revolutionary algorithm that does not resemble any previous known OOO superscalar design that has no temporary registers (not renaming, not re-order buffer).

Why: Dr Trang's lecture will illustrate the most important feature of this vector processor: its simplicity. The vector processor issues 8 micro-ops per cycle with up to 14 vector instructions in parallel execution.

Who should attend: SoC and ASIC chip architects, designers, and software developers.

When: Tuesday, July 13, 2021 at 09:00 AM Pacific Daylight Time.

Where: To attend the lecture, register at
Hope to see you there.


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