The 30th Annual DVCon U.S. Continues to be Must-Attend Conference for Design and Verification Engineers; Announces Best Paper Presentation & Best Poster Awards

Attendance boosted this year by new topic areas in program

LOUISVILLE, Colo., March 05, 2018 (GLOBE NEWSWIRE) -- The 2018 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative, concluded its 30th annual event last week with attendees energized by the many in-depth technical tutorials, panels, poster sessions and keynote address offered during the four-day program.  The DVCon Exposition was bustling each afternoon with many attendees meeting with experts and colleagues to connect and learn about the latest technologies to improve their design and verification productivity. 

Overall attendance, including exhibit-only and technical conference attendees, was 836.  Attendance was further enhanced by 241 exhibitor personnel that also had access to the panel sessions and keynote address, for a total of 1,077 participants. 

“We continually strive to improve the conference each year to give practicing design and verification engineers the latest and most valuable information on current and emerging standards under one roof over four days,” stated Dennis Brophy, DVCon U.S. General Chair. “We have grown to keep pace with the needs of our returning and new attendees and added some new topic areas this year such as automotive security and RISC-V that were very well-received.  In addition to the technical program, the Expo continues to bring people together to discuss the latest technologies and issues they face with exhibitors and their peers.  The floor was full each afternoon and the conversations were lively.”

The Award for Best Paper Presentation, as voted by conference attendees, went to Jeffery Vance, Jeffrey Montesano, Kevin Vasconcellos and Kevin Johnston from Verilab, Inc. for their presentation, “My Testbench Used to Break! Now it Bends: Adapting to Changing Design Configurations.”  Second place was awarded to Jeremy Ridgeway and Hoe Nguyen from Broadcom Limited for their presentation, “Error Injection in a Subsystem Level Constrained Random UVM Testbench,” and third place was awarded to Rajarshi Roy, Chinmay Duvedi, Saad Godil and Mark Williams from NVIDIA Corp. for their paper, “Deep Predictive Coverage Collection.”

Top honors for Best Poster went to Timothy Pertuit, Doug Gibson and David Lacey from Hewlett Packard Enterprise for their poster, “Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages.” Second place was awarded to Mandar Munishwar, Qualcomm, Inc., Sandeep Jana, Synopsys (India) Pvt. Ltd. Xiaolin Chen and Arunava Saha, Synopsys, Inc. for their poster, “Fast Track Formal Verification Signoff.” Third place was awarded to Gabriel Chidolue, Rohit Jain and Shobana Sudhakar from Mentor, A Siemens Business for their poster, “Tired of Slow Gate Level Design Verification? Use these Efficient Modelling Styles and Methodology.”

“Congratulations to our Best Paper and Best Poster Winners for 2018,” stated Tom Fitzpatrick, DVCon U.S. Program Chair.  "We are very proud of the caliber of material we continue to offer our attendees, and our winners exemplify the hard work and dedication to high quality, in-depth subject matter that helps to make DVCon U.S. a must-attend conference.  I would also like to thank the DVCon Technical Committee for their long hours and hard work to ensure that the material selected for our attendees is the best of the best.  We continue to receive many more submissions than we can accept, which gives us outstanding options to choose from.”

Highlights of the Week:

New vertical topics were added to the program this year, resulting in an increase in first-time attendees to the conference.  Many attendees were eager to attend Thursday sponsored tutorial sessions and learn more about ISO 26262 compliance and automotive security.  There were also a number of sessions throughout the week on Portable Stimulus, including the Monday morning tutorial from the Accellera Working Group that provided updates on the emerging standard to a full house.

Richard Weber, CEO of Semifore, Inc., was honored during the Accellera-sponsored luncheon on Monday as the recipient of the seventh annual Accellera Technical Excellence Award.  The Monday afternoon tutorial on UVM introduced a room full of engineers to the new reference implementation aligned with IEEE Std. 1800.2™-2017 created by the Accellera UVM Working Group.

On Tuesday Christopher Tice, vice president of Verification Continuum Solutions in the Verification Group at Synopsys, delivered the keynote addressing how new growth segments in the industry, such as Automotive, IoT, Networking, and 5G Mobile among others, are fundamentally changing the requirements for verification.   

There were two panels on Wednesday, the first panel, “Help! System Coverage is a Big Data Problem!” had panelists discussing options for system coverage and possible improvements.  The second panel, “The Right Tool (or Tools) for the Toughest Verification Tasks,” tackled how decisions are made about which tool or tools are best in a design verification flow.

Short workshops were added to the program this year to give smaller companies more opportunities to participate in DVCon. They were well-received by attendees looking to learn more about additional design and verification technologies and solutions in 90-minute segments not otherwise covered in the DVCon U.S. program.

The DVCon Steering Committee values all feedback regarding the conference.  Attendees have been given a survey and are asked to provide input on how to make DVCon U.S. 2019 even better.

Save the date:  DVCon U.S. 2019 will be held February 25-28, 2019 at the DoubleTree Hotel in San Jose, California. 

About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit For more information about DVCon U.S., please visit Follow DVCon on Facebook or @dvcon_us on Twitter or to comment, please use #dvcon_us.

For more information, please contact:
Nannette Jordan                                                         
MP Associates, Inc.                                                    

Barbara Benjamin
HighPointe Communications