UNITED STATES -- (MARKET WIRE) -- March 26, 2007 -- SINGAPORE -- 03/26/2007 -- STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (NASDAQ: STTS) (SGX-ST: STATSChP), a leading independent semiconductor test and advanced packaging service provider, today announced a new Fan-in Package on Package (FiPoP) solution which delivers increased functional integration in a smaller form factor, flexibility in stacking conventional memory packages on top, improved final assembly yields, and a lower overall cost as compared to conventional PoP solutions. FiPoP has a versatile design which accommodates multiple die and larger die sizes in a reduced footprint and the flexibility to stack off the shelf memory packages with center ball grid array patterns on the top surface.

PoP is a three dimensional (3D) package in which a fully tested package such as single die FBGA or stacked die FBGA (typically memory die) is stacked on a bottom PoP package which usually contains a logic device or logic device combination (logic + logic, logic + analog, etc.). In standard PoP package designs, the top PoP package is interconnected to the bottom PoP package through solder balls around the periphery of the bottom PoP package. Integration of multiple die and larger die sizes in the bottom PoP package has been constrained by the footprint and ball height of the top PoP package.

STATS ChipPAC's new Fan-in PoP solution opens up the range of integration options in the bottom PoP package while allowing greater freedom in stacking off the shelf memory packages on top. Fan-in PoP provides the flexibility to stack multiple logic, analog and memory die in the bottom PoP package and accommodates larger die sizes in a reduced footprint as compared to conventional PoP designs. The Fan-in PoP structure provides the unique advantage of being able to mount smaller conventional memory packages with center ball grid array patterns on top.

"Demand for greater functionality in a smaller size is a driving force in mobile applications. Conventional PoP has been adopted by handset makers to integrate logic and memory devices in a smaller footprint with higher test yields, configuration flexibility and lower overall cost of ownership. Building on the capabilities of PoP, Fan-in PoP expands the range of integration schemes available to customers in the bottom package and delivers a cost effective, high yield solution in a smaller package size, especially for the top memory package," said Dr. Han Byung Joon, STATS ChipPAC's Executive Vice President and Chief Technology Officer. "Depending on die size and complexity, Fan-in PoP can reduce the final form factor up to 25 percent in the bottom PoP package with a space savings of up to 65 percent in the top PoP package."

One of Fan-in PoP's key features is an exposed array of land pads on the top center surface of the package, instead of a peripheral array around the top of the bottom package substrate as found in a conventional PoP. This provides a flexible integration point for memory packages with a center ball grid array pattern.

STATS ChipPAC has developed two versions of Fan-in PoP. One version incorporates a fully tested Internal Stacking Module (ISM) package for integration of fully tested memory or other device types within the bottom package. The second version integrates probed good or known good die stacked in the bottom package. Conventional memory packages can be stacked on top of either Fan-in PoP design during the board mount process.

"High reflow temperatures during the surface mount process can often cause thin PoP packages to warp. The inherent design of the Fan-in PoP structure provides a more stable base that improves final assembly yields by eliminating warpage in the bottom package," continued Dr. Han. "When you look at the integration flexibility of Fan-in PoP combined with the increased yields and reduction in space required on the motherboard, Fan-in PoP clearly stands out as leading edge technology."

About STATS ChipPAC Ltd.

STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (NASDAQ: STTS) (SGX-ST: STATSChP) is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions. A trusted partner and supplier to leading semiconductor companies worldwide, STATS ChipPAC provides fully integrated, multi-site, end-to-end packaging and testing solutions that bring products to the market faster. Our customers are some of the largest wafer foundries, integrated device manufacturers (IDMs) and fabless companies in the United States, Europe and Asia. STATS ChipPAC is a leader in mixed signal testing and advanced packaging technology for semiconductors used in diverse end market applications including communications, power, digital consumer and computing. With advanced process technology capabilities and a global manufacturing presence spanning Singapore, South Korea, China, Malaysia and Taiwan, STATS ChipPAC has a reputation for providing dependable, high quality test and packaging solutions. The Company's customer support offices are centered in the United States (California's Silicon Valley, Arizona, Texas, Massachusetts, Colorado and North Carolina). Our offices outside the United States are located in South Korea, Singapore, China, Malaysia, Taiwan, Japan, the Netherlands and United Kingdom. STATS ChipPAC's facilities include those of its subsidiary, Winstek Semiconductor Corporation, in Hsinchu District, Taiwan. These facilities offer new product introduction support, pre-production wafer sort, final test, packaging and other high volume preparatory services. Together with our research and development centers in South Korea, Singapore, Malaysia, China, Taiwan and the United States as well as test facilities in the United States, this forms a global network providing dedicated test engineering development and product engineering support for customers from design to volume production. STATS ChipPAC is listed on both the Nasdaq Stock Market and the Singapore Exchange Securities Trading Limited. In addition, STATS ChipPAC is also included in the Morgan Stanley Capital International (MSCI) Index and the Straits Times Industrial Index. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.

Certain statements in this release, including statements regarding expected future financial results and industry growth, are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include general business and economic conditions and the state of the semiconductor industry; level of competition; demand for end-use applications products such as communications equipment and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; reliance on a small group of principal customers; continued success in technological innovations; availability of financing; pricing pressures including declines in average selling prices; tender offer by Singapore Technologies Semiconductors Pte Ltd, a subsidiary of Temasek Holdings (Private) Limited (Temasek Holdings); actions that may be taken by the Company or third parties in connection with or in response to such tender offer; our substantial level of indebtedness; potential impairment charges; adverse tax and other financial consequences if the South Korean taxing authorities do not agree with our interpretation of the applicable tax laws; ability to develop and protect our intellectual property; rescheduling or canceling of customer orders; changes in products mix; intellectual property rights disputes and litigation; capacity utilization; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; changes in customer order patterns; shortages in supply of key components; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; significant ownership by Temasek Holdings that may result in conflicting interests with Temasek Holdings and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; our ability to successfully integrate the operations of former STATS and ChipPAC and their employees; labor union problems in South Korea; uncertainties of conducting business in China; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; and other risks described from time to time in the Company's SEC filings, including its annual report on Form 20-F dated March 12, 2007. We undertake no obligation to publicly update or revise any forward-looking statements, whether as a result of new information, future events or otherwise.

Contact Information: Singapore Contact: Tham Kah Locke Tel: (65) 6824 7635 Fax: (65) 6720 7826 email: Email Contact US Contacts: Lisa Lavin Marcom Manager Tel: (208) 939 3104 Fax: (208) 939 4817 email: Email Contact The Ruth Group David Pasquale Executive Vice President Tel: (646) 536 7006 email: Email Contact