STATS ChipPAC Establishes R&D Facility for Next Generation Integration Technology

UNITED STATES -- (MARKET WIRE) -- May 14, 2007 -- SINGAPORE -- 05/14/2007 -- STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (NASDAQ: STTS) and (SGX-ST: STATSChP), a leading independent semiconductor test and advanced packaging service provider, today announced the establishment of a new research and development (R&D) facility located in Singapore which will be dedicated to developing next generation technology including through silicon via (TSV) and microbump bonding for three dimensional (3D) die, silicon substrate based packaging solutions, and embedded active die technology.

The new R&D facility includes over 10,000 square feet of Class 10, 100 and 10K cleanroom space with an additional 9,000 square feet of space available for future expansion. The R&D operation will specialize in wafer level processing with an equipment set for photolithography, plasma etching and deep reactive ion etching (DRIE), wafer thinning, and wafer bonding. A strong engineering workforce of 40 employees will focus on advanced wafer integration technology.

"As the semiconductor industry moves to finer pitch technology nodes to increase device functionality, performance and speed, there are technical challenges and performance limitations with standard packaging technology. How devices are stacked and interconnected has a significant impact on the size and performance of the final solution," said Dr. Han Byung Joon, STATS ChipPAC's Chief Technology Officer. "STATS ChipPAC has taken a leadership role in driving integration technology and flexibility in packaging architecture and we believe the next important step is to build on our 3D wafer level integration technology."

STATS ChipPAC was the first outsourced assembly and test provider to develop integrated passive devices (IPD) on a silicon substrate. Today, the Company offers customized silicon based solutions that include integrated passive networks such as baluns, filters, and amplifiers. The new R&D operation will expand on this technology to provide next generation IPDs as well as TSV and microbump bonding methods for 3D die and silicon substrate based system-in-package (SiP) solutions. TSV is the process of creating the contact via in silicon in order to establish an electrical connection from the active side to the backside of the die, thus creating options for 3D integration. Embedded die technologies are for next generation SiPs that enable a higher level of integration in a smaller form factor.

Dr. Han continued, "The new facility fulfills an important role in the Company's global R&D strategy and will augment our current worldwide R&D operations focusing on advanced packaging solutions."

About STATS ChipPAC Ltd.

STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (NASDAQ: STTS) and (SGX-ST: STATSChP) is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions. A trusted partner and supplier to leading semiconductor companies worldwide, STATS ChipPAC provides fully integrated, multi-site, end-to-end packaging and testing solutions that bring products to the market faster. Our customers are some of the largest wafer foundries, integrated device manufacturers (IDMs) and fabless companies in the United States, Europe and Asia. STATS ChipPAC is a leader in mixed signal testing and advanced packaging technology for semiconductors used in diverse end market applications including communications, power, digital consumer and computing. With advanced process technology capabilities and a global manufacturing presence spanning Singapore, South Korea, China, Malaysia and Taiwan, STATS ChipPAC has a reputation for providing dependable, high quality test and packaging solutions. The Company's customer support offices are centered in the United States (California's Silicon Valley, Arizona, Texas, Massachusetts, Colorado and North Carolina). Our offices outside the United States are located in South Korea, Singapore, China, Malaysia, Taiwan, Japan, the Netherlands and United Kingdom. STATS ChipPAC's facilities include those of its subsidiary, Winstek Semiconductor Corporation, in Hsinchu District, Taiwan. These facilities offer new product introduction support, pre-production wafer sort, final test, packaging and other high volume preparatory services. Together with our research and development centers in South Korea, Singapore, Malaysia, China, Taiwan and the United States as well as test facilities in the United States, this forms a global network providing dedicated test engineering development and product engineering support for customers from design to volume production. STATS ChipPAC is listed on both the Nasdaq Stock Market and the Singapore Exchange Securities Trading Limited. In addition, STATS ChipPAC is also included in the Morgan Stanley Capital International (MSCI) Index and the Straits Times Industrial Index. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.

Certain statements in this release, including statements regarding expected future financial results and industry growth, are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include general business and economic conditions and the state of the semiconductor industry; level of competition; demand for end-use applications products such as communications equipment and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; reliance on a small group of principal customers; continued success in technological innovations; availability of financing; pricing pressures including declines in average selling prices; tender offer by Singapore Technologies Semiconductors Pte Ltd, a subsidiary of Temasek Holdings (Private) Limited (Temasek Holdings); our substantial level of indebtedness; potential impairment charges; adverse tax and other financial consequences if the South Korean taxing authorities do not agree with our interpretation of the applicable tax laws; ability to develop and protect our intellectual property; rescheduling or canceling of customer orders; changes in products mix; intellectual property rights disputes and litigation; capacity utilization; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; changes in customer order patterns; shortages in supply of key components; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; significant ownership by Temasek Holdings that may result in conflicting interests with Temasek Holdings and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; our ability to successfully integrate the operations of former STATS and ChipPAC and their employees; labor union problems in South Korea; uncertainties of conducting business in China; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; and other risks described from time to time in the Company's SEC filings, including its annual report on Form 20-F dated March 12, 2007. We undertake no obligation to publicly update or revise any forward-looking statements, whether as a result of new information, future events or otherwise.

Contact Information: Singapore Contact: Tham Kah Locke Investor Relations Tel: (65) 6824 7635 Fax: (65) 6720 7826 email: Email Contact US Contacts: Lisa Lavin Marcom Manager Tel: (208) 939 3104 Fax: (208) 939 4817 email: Email Contact The Ruth Group David Pasquale Executive Vice President Tel: (646) 536 7006 email: Email Contact