OTTAWA--(Marketwire - May 13, 2008) - Sidense, a leading developer of Logic Non-Volatile Memory (LNVM) IP cores, today announced the Sidense Low Power (SLP) one-time programmable (OTP) memory macrocells for low-power and cost-sensitive applications that require highly secure information storage. Such applications include secure key storage, implantable medical devices, RFID, handheld wireless communication devices, analog trimming, and power and energy management.

Based on Sidense's patented split-channel architecture, SLP memory macro implementation requires no additional masks or process steps, thus adding no extra wafer processing cost. Implemented at 180nm, SLP macros are available in densities up to 256 kbits and multiple blocks may be stitched together for larger memory capacity. Power dissipation is very low, up to 80% lower power compared to competitive products, an important attribute for low power applications such as mobile devices. Typical read current for a 256 Kbit macro is 0.25uA/MHz/bit with a 2.5V read voltage. Macro sizes are also very small -- a 256 Kbit memory takes less than 0.5 mm-sq. of silicon.

"With Sidense's 1T-OTP SLP memory IP, our customers have a highly secure, very low-power embedded storage solution that offers low active and standby power and read access times below 50ns, ideal for power-sensitive devices," said Jim Lipman, Sidense's director of marketing. "In addition, SLP macros feature very small footprints, thus making them attractive for high-density storage applications."

Additional SLP Features

Since Sidense's 1T-OTP bit cells are not based on charge storage for bit programming, data retention is better than 20 years, making SLP macros a very reliable, long-term embedded storage solution. While SLP technology is one-time programmable, macros may be used in an emulated multi-time programmable (eMTP) mode through the use of uncommitted memory segments that can later be programmed in the field to update code, security key or other data storage.

SLP macros feature two additional read modes with enhanced margins and data security for highly reliable, field-programmable systems -- differential and redundant read modes. Differential read mode, available in a dual-array configuration only, compares two memory cells, one programmed and one un-programmed, without needing a reference. This provides faster read access times and improved voltage and temperature ranges, ideal for automotive applications. In redundant read mode, two memory cells that are programmed the same are accessed in parallel and compared to a reference voltage, doubling the array's signal margin.

Designers have an optional, configurable IPS (integrated power supply) macro available that can include a charge pump for field-programming SLP memory bits. The IPS macro can also supply the read reference voltage needed for non-differential read operations, eliminating the need for extra circuitry to supply a read reference voltage.

About Sidense

Sidense, listed on EE Times 60 Emerging Startups list for 2008, provides secure, dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes, with no additional masks or process steps required. Sidense's patented one-transistor 1T-Fuse™ architecture provides the industry's smallest footprint and lowest power Logic Non-Volatile Memory (NVM) solution.

Sidense OTP memory is available at 180nm, 130nm, 90nm and 65nm and scalable to 45nm and below. The IP is available at UMC, TSMC, SMIC, Tower and Chartered. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, visit

Contact Information: Media Contacts: Susan Cain Cain Communications for Sidense Tel: 503-538-2747 Email: Jim Lipman Sidense Tel: 925-606-1370 Email: