ALAMEDA, CA--(Marketwire - April 4, 2011) - Ausdia Inc., provider of chip design and closure solutions, has licensed Verific Design Automation's Verilog parser platform for use with its analysis and optimization software for accelerating timing constraint development, constraint validation and timing closure.

"When we looked for a platform for RTL analysis, we quickly realized that the only answer was Verific," says Sam Appleton, Ausdia's chief executive officer (CEO). "I can say without hesitation that this was a good move. Our customers know and recognize the value of Verific technology. Verific has been an exceptionally responsive vendor and the platforms it develops are top rate."

Originally, Ausdia's TimeVision operated at the netlist level using an internal solution. Ausdia turned to Verific for RTL code support, because Verific's parsers and elaborators have become the industry's de facto standard. Verific's Verilog and RTL elaborator and netlist parser have been integrated by Ausdia with TimeVision. Additionally, Ausdia has replaced its internal netlist data structures with those from Verific.

"Ausdia discovered, like so many other companies, that outsourcing front-end platforms makes good business sense," notes Michiel Ligthart, Verific's chief operating officer. "We've enjoyed working with the Ausdia team and look forward to a long relationship."

Since its founding in 1999, Verific's software has served as the front end to a wide range of Electronic Design Automation (EDA) and Field Programmable Gate Array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux, and Windows operating systems.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end software supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: www.verific.com.

Ausdia and Verific Design Automation acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

Contact Information:

For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822