ESD Alliance CEO Outlook 2019: eSilicon CEO Jack Harding to Participate

SAN JOSE, Calif., May 15, 2019 (GLOBE NEWSWIRE) -- eSilicon CEO Jack Harding will comment on the state of the application-specific integrated circuit (ASIC) market.

What
ESD Alliance CEO Outlook 2019 provides an opportunity to enjoy dinner, networking and a look into the future. Panelists: John Chong, VP, product and business development for Kionix; Jack Harding, president and CEO of eSilicon; John Kibarian, PDF Solutions’ president and CEO; and Wally Rhines, CEO emeritus of Mentor, a Siemens Business.

Each CEO will present a brief opening statement about the future of the industry, followed by an interactive audience discussion moderated by Ed Sperling, editor in chief, Semiconductor Engineering.

When
Thursday
May 23, 2019
5:30-8:30 PM

Agenda
5:30 PM check-in opens
6:00-7:00 PM networking, dinner and drinks
7:00-8:30 PM panel discussion

Where
SEMI
673 S. Milpitas Boulevard
Milpitas, Calif. 95035

Registration
Anyone who is part of the electronic system and semiconductor design ecosystem is welcome to attend free of charge; advance registration is required.

About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com

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