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Will Profile Speedcore eFPGA IP’s ability to add a programmable fabric to ASIC or SoC DesignsTwo IP Track Talks will feature presentations from Achronix’s Steve Mensor, Kent Orthner SANTA CLARA,...
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Steve Mensor to present “Embedded FPGA (eFPGA) for Processor and Algorithm Acceleration” at SEE/MAPLDWill highlight technology’s application for 5G wireless, HPC, ADAS and autonomous vehicles, machine...
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Will showcase its technology for 5G wireless, HPC, ADAS and autonomous vehicles, machine learning and computer vision applicationsSpeedcore eFPGA validation chip built on TSMC 16nm FinFET+ process...
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Move Designed to Accommodate 2018 Outlook, Growing Number of Employees to Support Technology Portfolio SANTA CLARA, Calif., April 25, 2018 (GLOBE NEWSWIRE) -- Achronix Semiconductor Corporation...
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CAST Compression IP Integrated with Achronix eFPGA Technology for High-Performance, Low-Power Solution to Move and Store Big Data SANTA CLARA, Calif., April 10, 2018 (GLOBE NEWSWIRE) -- Achronix...
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Will highlight its technology for 5G wireless, HPC, ADAS and autonomous vehicles, machine learning and computer vision applicationsAchronix Executive to Present “Embedded FPGA enabling the 5G...
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Will highlight its technology for military, aerospace and defense applications SANTA CLARA, Calif., March 08, 2018 (GLOBE NEWSWIRE) -- WHO: Achronix Semiconductor Corporation, a leader in field...
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AccelerComm’s Polar Code IP integrated with Achronix Portfolio of FPGA productsAchronix ACE design tools and AccelerComm IP integration targets Speedcore eFPGAs SANTA CLARA, Calif., Feb. 27,...
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Session Part of Day-Long Workshop Designed to Improve Information Sharing, Collaboration on eFPGA IP, Firmware AssuranceMITRE Corporation Hosts Event to be held February 27 SANTA CLARA, Calif., Feb. ...
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Speedcore Validation Chip Passes Rigorous Testing Suite and Verified as Fully FunctionalComplex Designs Run at 500MHz Across All Operating Conditions SANTA CLARA, Calif., Jan. 17, 2018 (GLOBE...