eSilicon to present power optimization paper at SNUG Singapore, September 21, 2018

Power Optimization for ASICs: Using Custom Low-Power Flops

San Jose, California, UNITED STATES

SAN JOSE, Calif., Sept. 17, 2018 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will present Power Optimization for ASICs: Using Custom Low-Power Flops, September 21 at SNUG Singapore.

Power Optimization for ASICs: Using Custom Low-Power Flops
The IC manufacturing process is evolving rapidly, increasing the complexity of chip design. A block of 2M gates in 14nm occupies ~1mm2 in silicon while the same block in 7nm takes up only 0.3mm2, tripling the amount of logic that can be implemented in the same area. However, voltage scaling does not follow the same trend. From 14nm to 7nm, the nominal voltage is only lowered by 10 percent, resulting in a much higher power density in 7nm. While leakage power has been reduced significantly due to technology improvements (FinFETs), dynamic power, especially in high-performance chips, has grown significantly and is currently one key limitation in building ASICs.

EDA tools are shifting towards optimization of dynamic power from the well-established leakage power optimization, but that is not enough to compensate for the trend and it is necessary to look for additional design methods to reduce chip power consumption.

Based on our designs we see that clock networks and, in particular, the power consumption of the flops is responsible for roughly 50 percent of total power consumption. For that reason, we have developed custom low-power flops to reduce overall chip power. These flops have been optimized for low power while still retaining good performance. However, since they are slower than performance-optimized flops it is necessary to use them properly to meet the performance requirements of high-performance chips.

In this paper we present a methodology to make optimal use of our low-power flops without compromising the design performance using IC Compiler II. Using proprietary flops and the methodology presented here we can reduce power by around 15 percent without degrading the design performance.

Tinh Ho Nam, manager, ASIC engineering, eSilicon and Hieu Vo Quang, ASIC design engineer, eSilicon

Friday, September 21, 2018


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eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets.

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